Integrated fan-out package and method of fabricating the same

ABSTRACT

An integrated fan-out package including a chip module, a second integrated circuit, a second insulating encapsulation, and a redistribution circuit structure is provided. The chip module includes a first insulating encapsulation and a first integrated circuit embedded in the first insulating encapsulation, and the first integrated circuit includes a first surface and first conductive terminals on the first surface. The second integrated circuit includes a second surface and second conductive terminals on the second surface. The chip module and the second integrated circuit are embedded in the second insulating encapsulation. The first and second conductive terminals are accessibly exposed from the first and second insulating encapsulation. The redistribution circuit structure covers the first surface, the second surfaces, the first insulating encapsulation, and the second insulating encapsulation. The redistribution circuit structure is electrically connected to the first and second conductive terminals. Methods of fabricating the integrated fan-out package are also provided.

BACKGROUND

The semiconductor industry has experienced rapid growth due tocontinuous improvements in the integration density of various electroniccomponents (i.e., transistors, diodes, resistors, capacitors, etc.). Forthe most part, this improvement in integration density has come fromrepeated reductions in minimum feature size, which allows more of thesmaller components to be integrated into a given area. These smallerelectronic components also require smaller packages that utilize lessarea than previous packages. Some smaller types of packages forsemiconductor components include quad flat packages (QFPs), pin gridarray (PGA) packages, ball grid array (BGA) packages, and so on.

Currently, integrated fan-out packages are becoming increasingly popularfor their compactness. In the integrated fan-out packages includingmultiple chips that are encapsulated by the molding compound,reliability of electrical connection between the chips and theredistribution circuit structure fabricated on the molding compound maydeteriorate due to thickness difference between the chips. How toincrease yield rate of the fabrication of integrated fan-out packages ishighly concerned.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1A through 1E illustrate a process flow for fabricating a chipmodule in accordance with some embodiments.

FIGS. 2A through 2E illustrate another process flow for fabricating achip module in accordance with some embodiments.

FIGS. 3A through 3E illustrate yet another process flow for fabricatinga chip module in accordance with some embodiments.

FIGS. 4 through 10 are cross-sectional views illustrating a process flowfor fabricating an integrated fan-out package in accordance with someembodiments.

FIGS. 11 through 13 are cross-sectional views illustrating variousintegrated fan-out packages in accordance with various embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

FIGS. 1A through 1E illustrate a process flow for fabricating a chipmodule in accordance with some embodiments. Referring to FIG. 1A, aplurality of first integrated circuits 110 are provided and mounted ontoa substrate SUB through an adhesive AD between the first integratedcircuits 110 and the substrate SUB. In some embodiments, the substrateSUB is a glass substrate, and the adhesive AD is a light-to-heatconversion (LTHC) release layer formed on the glass substrate. However,the materials of the adhesive AD and the substrate SUB are merely forillustration, and the disclosure is not limited thereto.

As shown in FIG. 1A, in some embodiments, each of the first integratedcircuits 110 includes a first surface 112 and a plurality of firstconductive terminals 114 distributed on the first surface 112. The firstsurfaces 112 are active surfaces of the first integrated circuits 110.The first integrated circuits 110 are flipped onto the adhesive AD suchthat the first surfaces 112 may face the substrate SUB. The firstsurfaces 112 of the first integrated circuits 110 are in contact withthe adhesive AD, and the first conductive terminals 114 of the firstintegrated circuits 110 are embedded in the adhesive AD. In someembodiments, the first conductive terminals 114 may be conductivepillars, conductive bumps, or conductive vias. For example, the firstconductive terminals 114 are plated copper pillars, plated copper bumps,or plated copper vias. After first integrated circuits 110 are flippedonto the adhesive AD, the first surfaces 112 of first integratedcircuits 110 are coplanar with one another.

In some embodiments, the first integrated circuits 110 may be fabricatedby different third parties and have various thicknesses. Even though thefirst integrated circuits 110 are fabricated by the same party,different batches of the first integrated circuits 110 may still havethickness variation. In order to minimize the thickness variation ordifference of the first integrated circuits 110, a thickness levelingprocess as illustrated in FIGS. 1B through 1E is required to beperformed.

Referring to FIG. 1B, an insulating material 120 a is formed on theadhesive AD to encapsulate the first integrated circuits 110 to form apre-molded structure P. The first integrated circuits 110 are sandwichedbetween the insulating material 120 a and the adhesive AD. In someembodiments, the insulating material 120 a is a molding compound formedby a molding process. The rear surfaces and sidewalls of the firstintegrated circuits 110 are encapsulated by the insulating material 120a. In other words, the first integrated circuits 110 are protected bythe insulating material 120 and the adhesive AD. In some embodiments,the insulating material 120 a includes epoxy or other suitable resins.

As shown in FIG. 1B, the pre-molded structure P1 includes the insulatingmaterial 120 a (e.g., the afore-said molding compound) and the firstintegrated circuits 110 embedded in the insulating material 120 a.

Referring to FIG. 1C, after the insulating material 120 a (e.g., theafore-said molding compound) is formed, a grinding process is performedto reduce the thickness of the pre-molded structure P1. In someembodiments, as shown in FIG. 1C, the insulating material 120 a and thefirst integrated circuits 110 are grinded until the rear surfaces of allthe first integrated circuits 110 are exposed. After the grindingprocess is performed, the grinded first integrated circuits 110 aresubstantially identical in thickness, the insulating material 120 a isgrinded to form an insulating material 120 b, and the grinded firstintegrated circuits 110 are encapsulated by the insulating material 120b.

In some embodiments, the insulating material 120 a is grinded throughmechanical grinding process and/or chemical mechanical polishing (CMP)process, for example.

After the grinding process is performed, a grinded pre-molded structureP2 is formed. The grinded pre-molded structure P2 includes theinsulating material 120 b (e.g., a grinded molding compound) and thefirst integrated circuits 110 embedded in the insulating material 120 b.In some embodiments, as shown in FIG. 1C, the first integrated circuits110 and the insulating material 120 b are substantially identical inthickness. Due to the above-mentioned grinding process, the thicknessvariation or thickness difference of the first integrated circuits 110in the pre-molded structure P2 are minimized.

In some embodiments, the insulating material 120 a (shown in FIG. 1B) isgrinded such that the thickness of the grinded pre-molded structure P2(shown in FIG. 1C) is substantially equal to the thickness of the secondintegrated circuit 200 (shown in FIG. 5).

Referring to FIG. 1D, the pre-molded structure P2 is de-bonded from theadhesive AD carried by the substrate SUB. In some embodiments, theadhesive AD (e.g., the LTHC release layer) may be irradiated by an UVlaser such that the pre-molded structure P2 is peeled from the adhesiveAD and the substrate SUB.

After the pre-molded structure P2 is de-bonded from the adhesive AD, adielectric material 130 is formed on the pre-molded structure P2 tocover the first surfaces 112 and the first conductive terminals 114 offirst integrated circuits 110. As shown in FIG. 1D, the first surfaces112 and the first conductive terminals 114 are protected by thedielectric material 130. In some embodiments, the dielectric material130 is a polybenzoxazole (PBO) layer or other suitable polymerdielectrics, for example.

Referring to FIG. 1E, after the dielectric material 130 is formed on thepre-molded structure P2, the pre-molded structure P2 and the dielectricmaterial 130 are placed on a tape TP supported by a holder H. In someembodiments, the tape TP may be a die-saw tape adhered with thepre-molded structure P2, the holder H may be a frame having an aperture,and the tape TP is fixed in the aperture of the holder H. The pre-moldedstructure P2 and the dielectric material 130 are then singulated to forma plurality of chip modules 100 and/or multi-chip modules 100A. Afterthe singulation process is performed, the chip modules 100 and/ormulti-chip modules 100A are still adhered with the tape TP.

The pre-molded structure P2 and the dielectric material 130 aresingulated through a die saw process, for example. After the insulatingmaterial 120 b of the pre-molded structure P2 is cut, a plurality offirst insulating encapsulation 120 c for encapsulating sidewalls of thefirst integrated circuits 110 are formed. After the dielectric material130 is cut, a plurality of first dielectric layers 130 a (e.g., apolybenzoxazole layer) are formed to cover the first surfaces 112 of thefirst integrated circuits 110, top surfaces of the first insulatingencapsulation 120 c, and the first conductive terminals 114. In somealternative embodiments, the dielectric material 130 and the dielectriclayers 130 a may be omitted in accordance with design requirements. Inother words, the first surfaces 112 of the first integrated circuits 110and the first conductive terminals 114 are accessibly exposed from thedielectric material 130.

As shown in FIG. 1E, different types of chip modules (e.g., the chipmodules 100 and the multi-chip modules 100A) are fabricated. Thethickness of chip modules 100 and the multi-chip modules 100A issubstantially equal to the thickness of the second integrated circuit200 (shown in FIG. 5). In the chip module 100, merely one integratedcircuit 110 is embedded in the first insulating encapsulation 120 c. Inother words, the first insulating encapsulation 120 c of the chip module100 includes one first through hole TH for accommodating the firstintegrated circuit 110. In the multi-chip module 100A, two integratedcircuits 110 are embedded in the first insulating encapsulation 120 c.In other words, the first insulating encapsulation 120 c of themulti-chip module 100A includes two first through holes TH foraccommodating the first integrated circuits 110. The number of the firstthrough holes TH is corresponding to the number of the first integratedcircuits 110.

As shown in FIG. 1B through 1E, after the above-mentioned thicknessleveling process is accomplished, the thickness variation or thicknessdifference of the chip modules 100 and/or the multi-chip module 100A canbe minimized.

FIGS. 2A through 2E illustrate another process flow for fabricating achip module in accordance with some embodiments. Referring to FIGS. 1Athrough 1E and FIGS. 2A through 2E, the fabricating process illustratedin FIGS. 2A through 2E is similar with the fabricating process describedin FIGS. 1A through 1E except that the formation of the grindedpre-molded structure P2′, as shown in FIG. 2C.

Referring to FIG. 2B and FIG. 2D, the pre-molded structure P1 is grindedto form a grinded pre-molded structure P2′. Specifically, the insulatingmaterial 120 a is grinded to form an insulating material 120 b′ (shownin FIGS. 2C and 2D), and the rear surfaces of all the first integratedcircuits 110 are not revealed after the insulating material 120 a isgrinded. In some embodiments, the insulating material 120 a (shown inFIG. 2B) is grinded such that the thickness of the grinded pre-moldedstructure P2′ (shown in FIG. 2C) is substantially equal to the thicknessof the second integrated circuit 200 (shown in FIG. 5).

In some alternative embodiments, the grinding process of the pre-moldedstructure P1 may be omitted. In other words, the thickness of theinsulating material 120 a is substantially equal to the thickness of thesecond integrated circuit 200 (shown in FIG. 5), and no further grindingprocess is required to be performed to reduce the thickness of theinsulating material 120 a.

Referring to FIG. 2E, after the dielectric material 130 is formed on thepre-molded structure P2′, the pre-molded structure P2′ and thedielectric material 130 are placed on a tape TP supported by a holder H.In some embodiments, the tape TP may be a die-saw tape adhered with thepre-molded structure P2′, the holder H may be a frame having anaperture, and the tape TP is fixed in the aperture of the holder H. Thepre-molded structure P2′ and the dielectric material 130 are thensingulated to form a plurality of chip modules 100B, chip modules 100Cand/or multi-chip modules 100D. After the singulation process isperformed, the chip modules 100B, chip modules 100C and/or multi-chipmodules 100D are still adhered with the tape TP.

The pre-molded structure P2′ and the dielectric material 130 aresingulated through a die saw process, for example. After the insulatingmaterial 120 b′ of the pre-molded structure P2′ is cut, a plurality offirst insulating encapsulation 120 c′ for encapsulating sidewalls of thefirst integrated circuits 110 are formed. After the dielectric material130 is cut, a plurality of first dielectric layers 130 a are formed tocover the first surfaces 112 of the first integrated circuits 110, topsurfaces of the first insulating encapsulation 120 c′, and the firstconductive terminals 114. In some alternative embodiments, thedielectric material 130 and the dielectric layers 130 a may be omittedin accordance with design requirements. In other words, the firstsurfaces 112 of the first integrated circuits 110 and the firstconductive terminals 114 are accessibly exposed from the dielectricmaterial 130.

As shown in FIG. 2E, different types of chip modules (e.g., the chipmodules 100B, the chip modules 100C and/or the multi-chip modules 100D)are fabricated. The thickness of the chip modules 100B, the chip modules100C, and the multi-chip modules 100D is substantially equal to thethickness of the second integrated circuit 200 (shown in FIG. 5). In thechip module 100B and the chip module 100C, merely one integrated circuit110 is embedded in the first insulating encapsulation 120 c′, and thefirst insulating encapsulation 120 c′ of the chip module 100B and thechip module 100C respectively includes one cavity CV for accommodatingthe first integrated circuit 110. The depth of the cavity CV is lessthan a thickness of the first insulating encapsulation 120 c′.Furthermore, the cavity CV in the chip module 100B may be different fromthe cavity CV in the chip module 100C, while the thickness of theintegrated circuit 110 in the chip module 100B may be different from thethickness of the integrated circuit 110 in the chip module 100C.

In the multi-chip module 100D, two integrated circuits 110 are embeddedin the first insulating encapsulation 120 c′, and the first insulatingencapsulation 120 c′ of the multi-chip module 100D includes two cavitiesCV for accommodating the first integrated circuits 110. In someembodiments, the cavities CV in the multi-chip module 100D may bedifferent in depth, the depths of the cavities CV are less than athickness of the first insulating encapsulation 120 c′, and thethickness of the integrated circuits 110 in the multi-chip module 100Dmay be different from each other. The number of the cavities CV iscorresponding to the number of the first integrated circuits 110.

FIGS. 3A through 3E illustrate yet another process flow for fabricatinga chip module in accordance with some embodiments. Referring to FIGS. 2Athrough 2E and FIGS. 3A through 3E, the fabricating process illustratedin FIGS. 3A through 3E is similar with the fabricating process describedin FIGS. 2A through 2E except that the formation of the grindedpre-molded structure P2″, as shown in FIG. 3C.

Referring to FIG. 3B and FIG. 3D, the pre-molded structure P1 is grindedto form a grinded pre-molded structure P2″. Specifically, the insulatingmaterial 120 a is grinded to form an insulating material 120 b″ (shownin FIGS. 3C and 3D), and the rear surfaces of parts of the firstintegrated circuits 110 are revealed after the insulating material 120 ais grinded. In some embodiments, the insulating material 120 a (shown inFIG. 3B) is grinded such that the thickness of the grinded pre-moldedstructure P2″ (shown in FIG. 3C) is substantially equal to the thicknessof the second integrated circuit 200 (shown in FIG. 5).

Referring to FIG. 3E, after the dielectric material 130 is formed on thepre-molded structure P2″, the pre-molded structure P2″ and thedielectric material 130 are placed on a tape TP supported by a holder H.In some embodiments, the tape TP may be a die-saw tape adhered with thepre-molded structure P2″, the holder H may be a frame having anaperture, and the tape TP is fixed in the aperture of the holder H. Thepre-molded structure P2″ and the dielectric material 130 are thensingulated to form a plurality of multi-chip modules 100E. After thesingulation process is performed, the multi-chip modules 100E are stilladhered with the tape TP.

The pre-molded structure P2″ and the dielectric material 130 aresingulated through a die saw process, for example. After the insulatingmaterial 120 b″ of the pre-molded structure P2″ is cut, a plurality offirst insulating encapsulation 120 c″ for encapsulating at leastsidewalls of the first integrated circuits 110 are formed. After thedielectric material 130 is cut, a plurality of first dielectric layers130 a are formed to cover the first surfaces 112 of the first integratedcircuits 110, top surfaces of the first insulating encapsulation 120 c″,and the first conductive terminals 114. In some alternative embodiments,the dielectric material 130 and the dielectric layers 130 a may beomitted in accordance with design requirements. In other words, thefirst surfaces 112 of the first integrated circuits 110 and the firstconductive terminals 114 are accessibly exposed from the dielectricmaterial 130.

As shown in FIG. 3E, the thickness of the multi-chip modules 100E issubstantially equal to the thickness of the second integrated circuit200 (shown in FIG. 5). In the multi-chip module 100E, two integratedcircuits 110 having various thicknesses are embedded in the firstinsulating encapsulation 120 c″, and the first insulating encapsulation120 c″ includes one cavity CV and a first through hole TH foraccommodating the first integrated circuits 110. The depth of the cavityCV is less than a thickness of the first insulating encapsulation 120c″. The total number of the cavity CV and the first through hole TH iscorresponding to the number of the first integrated circuits 110.

FIGS. 4 through 10 are cross-sectional views illustrating a process flowfor fabricating an integrated fan-out package in accordance with someembodiments.

Referring to FIG. 4, a carrier C having a de-bonding layer DB formedthereon is provided. The de-bonding layer DB is formed on an uppersurface of the carrier C, for example. In some embodiments, the carrierC is a glass substrate, and the de-bonding layer DB is a light-to-heatconversion (LTHC) release layer formed on the glass substrate. However,the materials of the de-bonding layer DB and the carrier C are merelyfor illustration, and the disclosure is not limited thereto.

Referring to FIG. 5, at least one chip module 100 and a secondintegrated circuit 200 are placed on the de-bonding layer DB carried bythe carrier C. In FIG. 5, two chip modules 100 are placed on thede-bonding layer DB. However, the number of the chip modules 100 ismerely for illustration, and the disclosure is not limited thereto. Insome alternative embodiments, before the chip modules 100 and the secondintegrated circuit 200 are picked-up and placed on the de-bonding layerDB, a dielectric material (not shown) may be formed on the de-bondinglayer DB. In some embodiments, the dielectric material is apolybenzoxazole (PBO) layer or other suitable polymer dielectrics, forexample.

As shown in FIG. 5, the chip module 100 and the second integratedcircuit 200 are substantially identical in thickness. In other words,the first conductive terminals 114 and the second conductive terminals204 are substantially leveled with each other. The second integratedcircuit 200 includes a second surface 202 and a plurality of secondconductive terminals 204 distributed on the second surface 202. In someembodiments, the first surfaces 112 of the first integrated circuits 110in the chip modules 100 are substantially coplanar with the secondsurface 202 of the second integrated circuit 200. Furthermore, theheight of the first conductive terminals 114 is substantially equal tothe height of the second conductive terminals 204, for example.

The first surfaces 112 of the first integrated circuits 110 isencapsulated by the first dielectric layers 130 a, and the secondsurface 202 of the second integrated circuit 200 is encapsulated by asecond dielectric layer 210. The second conductive terminals 204distributed on the second surface 202 are covered and protected by thesecond dielectric layer 210. In some embodiments, the first dielectriclayers 130 a and the second dielectric layer 210 are substantiallyidentical in thickness. The material of the second dielectric layer 210is a polybenzoxazole (PBO) layer or other suitable polymer dielectrics,for example. Furthermore, the material of the second dielectric layer210 may be the same as or different from the material of the firstdielectric layers 130 a. In some alternative embodiments, the formationof the dielectric layers 130 and the second dielectric layer 210 may beomitted in accordance with design requirements. In yet alternativeembodiments, the formation of the dielectric layers 130 or the seconddielectric layer 210 may be omitted in accordance with designrequirements. In other words, merely the first dielectric layers 130 orthe second dielectric layer 210 may be formed.

Referring to FIG. 6, an insulating material 220 is formed on thede-bonding layer DB carried by the carrier C so as to encapsulate thechip modules 100 and the second integrated circuit 200. As shown in FIG.6, the first dielectric layers 130 a and the second dielectric layer 210are encapsulated by the insulating material 220, the first dielectriclayers 130 a are between the insulating material 220 and the chipmodules 100, and the second dielectric layer 210 is between theinsulating material 220 and the second integrated circuit 200. In someembodiments, the insulating material 220 is a molding compound formed bya molding process.

Referring to FIG. 7, the insulating material 220, the first dielectriclayers 130 a, and the second dielectric layer 210 are grinded until thetop surfaces of the first conductive terminals 114 and the top surfacesof the second conductive terminals 204 are exposed. After the insulatingmaterial 220, the first dielectric layers 130 a, and the seconddielectric layer 210 are grinded, the second insulating encapsulation220 a is formed on the carrier C. The first conductive terminals 114 andthe second conductive terminals 204 are accessibly exposed from thefirst insulating encapsulation 120 c and the second insulatingencapsulation 220 a.

After the insulating material 220, the first dielectric layers 130 a,and the second dielectric layer 210 are grinded, the first dielectriclayers 130 a is partially removed to form a first dielectric layers 130a′, and the second dielectric layer 210 is partially removed to form asecond dielectric layer 210′. As shown in FIG. 7, after the grindingprocess is performed, the first conductive terminals 114 are laterallyencapsulated by the first dielectric layer 130 a′, and the secondconductive terminals 204 are laterally encapsulated by the seconddielectric layer 210′. In addition, the thickness of the secondinsulating encapsulation 220 a is greater than the thickness of thefirst insulating encapsulation 120 c.

As shown in FIG. 7, the second insulating encapsulation 220 a at leastencapsulates the sidewalls of the chip modules 100 and the sidewalls ofthe second integrated circuit 200. Since the second insulatingencapsulation 220 a and the first insulating encapsulations 120 c of thechip modules 100 are fabricated by different molding processesrespectively, interfaces are formed between the second insulatingencapsulation 220 a and the first insulating encapsulations 120 c. Thesecond insulating encapsulation 220 a may further encapsulate thesidewalls of the first dielectric layers 130 a′ and the sidewalls of thesecond dielectric layers 210′. In addition, the second insulatingencapsulation 220 a includes a plurality of second through holes TH′ foraccommodating the chip module 100 and the second integrated circuit 200.

As shown in FIG. 7, it is noted that the top surfaces of the firstconductive terminals 114, the top surfaces of the second conductiveterminals 204, the exposed surface of the first dielectric layers 130a′, and the exposed surface of the second dielectric layers 210′ aresubstantially coplanar.

Referring to FIG. 8, after the second insulating encapsulation 220 a isformed, a redistribution circuit structure 230 electrically connected tothe first conductive terminals 114 of the chip module 100 and the secondconductive terminals 204 of the second integrated circuit 200 is formed.The redistribution circuit structure 230 is formed on the exposedsurface of the first dielectric layers 130 a′, the exposed surface ofthe second dielectric layers 210′, and the top surface of the secondinsulating encapsulation 220 a.

As shown in FIG. 8, the first dielectric layer 130 a′ is between thefirst surface 112 of the first integrated circuit 110 and theredistribution circuit structure 230, and the second dielectric layer210′ is between the second surface 202 of the second integrated circuit200 and the redistribution circuit structure 230. In other words, theredistribution circuit structure 230 is formed above the first surface112 of the first integrated circuits 110, the second surface 202 of thesecond integrated circuit 200, and the first insulating encapsulation120 c. Furthermore, the redistribution circuit structure 230 is incontact with the second insulating encapsulation 220 a.

Referring to FIG. 9, after the redistribution circuit structure 230 isformed, a plurality of conductive balls or bumps 240 and/or a pluralityof passive components 250 are placed on and are electrically connectedto the redistribution circuit structure 230. In some embodiments, theconductive balls or bumps 240 may be placed on the redistributioncircuit structure 230 by ball placement process and reflow process, andthe passive components 250 may be mounted on the redistribution circuitstructure 230 through reflow process. In some alternative embodiments,the conductive balls or bumps 240 may be controlled collapse chipconnection (i.e. C4) bumps or copper pillars.

Referring to FIG. 10, after the conductive balls or bumps 240 and/or thepassive components 250 are mounted, the de-bonding layer DB is de-bondedfrom the chip modules 100, the second integrated circuit 200, and thesecond insulating encapsulation 220 a. In some embodiments, thede-bonding layer DB (e.g., the LTHC release layer) may be irradiated byan UV laser such that the de-bonding process is facilitated.

FIGS. 11 through 13 are cross-sectional views illustrating variousintegrated fan-out packages in accordance with various embodiments.Referring to FIG. 11, the integrated fan-out package includes two chipmodules 100, a second integrated circuit 200, a second insulatingencapsulation 220 a, and a redistribution circuit structure 230. Each ofthe chip modules 100 includes a first insulating encapsulation 120 c andat least one first integrated circuit 110 embedded in the firstinsulating encapsulation 120 c. Each of the first integrated circuits110 includes a first surface 112 and a plurality of first conductiveterminals 114 distributed on the first surface 112. The secondintegrated circuit 200 includes a second surface 202 and a plurality ofsecond conductive terminals 204 distributed on the second surface 202.The chip module 100 and the second integrated circuit 200 are embeddedin the second insulating encapsulation 220 a. The first conductiveterminals 114 and the second conductive terminals 204 are accessiblyexposed from the first insulating encapsulation 120 c and the secondinsulating encapsulation 220 a. The redistribution circuit structure 230covers the first surface 112, the second surface 202, the firstinsulating encapsulation 112 c, and the second insulating encapsulation220 a. The redistribution circuit structure 230 is electricallyconnected to the first conductive terminals 114 and the secondconductive terminals 204.

Referring to FIG. 11 through FIG. 13, the integrated fan-out packagesillustrated in FIGS. 12 and 13 are similar with the integrated fan-outpackage illustrated in FIG. 11. In the integrated fan-out packageillustrated in FIG. 12, the chip modules 100 and 100C are used. In theintegrated fan-out package illustrated in FIG. 13, the chip modules 100Band 100C are used.

In some alternative embodiments, the integrated fan-out package maymerely include one chip module, and the chip module may be the chipmodule 100, the multi-chip module 100A, the chip module 100B, the chipmodule 100C, the multi-chip module 100D, and the chip module 100E. Inyet alternative embodiments, the integrated fan-out package may includetwo or more than two chip modules, and the chip modules may be selectedfrom the chip module 100, the multi-chip module 100A, the chip module100B, the chip module 100C, the multi-chip module 100D, and the chipmodule 100E.

In the above-mentioned embodiments, the thickness variation ordifference of the first integrated circuits 110 can be minimized throughthe thickness leveling process. Accordingly, the above-mentionedintegrated fan-out packages have good reliability and yield rate.

In accordance with some embodiments of the present disclosure, anintegrated fan-out package including a chip module, a second integratedcircuit, a second insulating encapsulation, and a redistribution circuitstructure is provided. The chip module includes a first insulatingencapsulation and at least one first integrated circuit embedded in thefirst insulating encapsulation. The first integrated circuit includes afirst surface and a plurality of first conductive terminals distributedon the first surface. The second integrated circuit includes a secondsurface and a plurality of second conductive terminals distributed onthe second surface. The chip module and the second integrated circuitare embedded in the second insulating encapsulation. The firstconductive terminals and the second conductive terminals are accessiblyexposed from the first insulating encapsulation and the secondinsulating encapsulation. The redistribution circuit structure coversthe first surface, the second surface, the first insulatingencapsulation, and the second insulating encapsulation. Theredistribution circuit structure is electrically connected to the firstconductive terminals and the second conductive terminals.

In accordance with alternative embodiments of the present disclosure, amethod of fabricating an integrated fan-out package is provided. Themethod includes the following steps. At least one chip module includinga first insulating encapsulation and at least one first integratedcircuit embedded in the first insulating encapsulation is provided,wherein the at least one first integrated circuit includes a firstsurface and a plurality of first conductive terminals distributed on thefirst surface. A second integrated circuit including a second surfaceand a plurality of second conductive ten finals distributed on thesecond surface is provided. The at least one chip module and the secondintegrated circuit are placed on a carrier with the first conductiveterminals and the second conductive terminals substantially leveled witheach other. A second insulating encapsulation is formed on the carrierto encapsulate sidewalls of the at least one chip module and sidewallsof the second integrated circuit. A redistribution circuit structure isformed on the at least one chip module, the second insulatingencapsulation, and the second integrated circuit. The redistributioncircuit structure is electrically connected to the first conductiveterminals and the second conductive terminals.

In accordance with yet alternative embodiments of the presentdisclosure, another method of fabricating an integrated fan-out packageis provided. The method includes the following steps. A plurality offirst integrated circuits are mounted on a substrate through anadhesive. Each of the first integrated circuits includes a first surfacefacing the substrate and a plurality of first conductive terminalsdistributed on the first surface. The first integrated circuits areencapsulated with a molding compound to form a pre-molded structure. Thepre-molded structure is de-bonded from the adhesive. The pre-moldedstructure is singulated to form a plurality of chip modules, and each ofthe chip modules includes at least one of the first integrated circuits.At least one of the chip modules is provided on a carrier having ade-bonding layer disposed thereon. The at least one chip module includesa first insulating encapsulation and at least one first integratedcircuit embedded in the first insulating encapsulation. The secondintegrated circuit includes a second surface and a plurality of secondconductive terminals distributed on the second surface, and the firstconductive terminals and the second conductive terminals aresubstantially leveled with each other. A second insulating encapsulationis formed on the de-bonding layer to encapsulate sidewalls of the atleast one chip module and sidewalls of the second integrated circuit. Aredistribution circuit structure is formed on the at least one chipmodule, the second insulating encapsulation, and the second integratedcircuit. The redistribution circuit structure is electrically connectedto the first conductive terminals and the second conductive terminals.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method of fabricating an integrated fan-outpackage, the method comprising: providing at least one chip modulecomprising a first insulating encapsulation and at least one firstintegrated circuit embedded in the first insulating encapsulation, theat least one first integrated circuit comprising a first active surface,a first rear surface opposite to the first active surface, and aplurality of first conductive terminals distributed on the first activesurface; providing a second integrated circuit, the second integratedcircuit comprising a second active surface, a second rear surfaceopposite to the second active surface, and a plurality of secondconductive terminals distributed on the second active surface; placingthe at least one chip module and the second integrated circuit on acarrier with the first conductive terminals and the second conductiveterminals substantially leveled with each other, wherein the first rearsurface and the second rear surface face the carrier; forming a secondinsulating encapsulation on the carrier to encapsulate sidewalls of theat least one chip module and sidewalls of the second integrated circuit;and forming a redistribution circuit structure on the at least one chipmodule, the second insulating encapsulation, and the second integratedcircuit, wherein the redistribution circuit structure is electricallyconnected to the first conductive terminals and the second conductiveterminals.
 2. The method of claim 1, wherein providing the chip modulecomprises: mounting a plurality of first integrated circuits on asubstrate through an adhesive between the first integrated circuits andthe substrate, and each of the first integrated circuits comprising thefirst active surface and the first conductive terminals; encapsulatingthe first integrated circuits by a molding compound to form a pre-moldedstructure, and the pre-molded structure comprising the molding compoundand the first integrated circuits embedded in the molding compound;de-bonding the pre-molded structure from the adhesive; and singulatingthe pre-molded structure to form a plurality of chip modules, whereineach of the chip modules comprises at least one of the first integratedcircuits.
 3. The method of claim 1, wherein providing the chip modulecomprises: mounting a plurality of first integrated circuits on asubstrate through an adhesive between the first integrated circuits andthe substrate, and each of the first integrated circuits comprising thefirst active surface and the first conductive terminals; encapsulatingthe first integrated circuits by a molding compound to form a pre-moldedstructure, and the pre-molded structure comprising the molding compoundand the first integrated circuits embedded in the molding compound;grinding the molding compound until a thickness of the pre-moldedstructure is substantially equal to a thickness of the second integratedcircuit; de-bonding the pre-molded structure from the adhesive; andsingulating the pre-molded structure to form a plurality of chipmodules, wherein each of the chip modules comprises at least one of thefirst integrated circuits.
 4. The method of claim 3, wherein the firstintegrated circuits are encapsulated by the molding compound and atleast parts of the first integrated circuits are exposed after grindingthe molding compound.
 5. The method of claim 3, wherein the at least onechip module and the second integrated circuit one the carrier areidentical in thickness.
 6. A method of fabricating an integrated fan-outpackage, the method comprising: mounting a plurality of first integratedcircuits on a substrate through an adhesive, each of the firstintegrated circuits comprising a first active surface facing thesubstrate, a first rear surface opposite to the first active surface anda plurality of first conductive terminals distributed on the firstactive surface; encapsulating the first integrated circuits with amolding compound to form a pre-molded structure; de-bonding thepre-molded structure from the adhesive; singulating the pre-moldedstructure to form a plurality of chip modules, each of the chip modulescomprising at least one of the first integrated circuits; providing atleast one of the chip modules and a second integrated circuit on acarrier having a de-bonding layer disposed thereon, the at least onechip module comprising a first insulating encapsulation and at least onefirst integrated circuit embedded in the first insulating encapsulation,the second integrated circuit comprising a second active surface, asecond rear surface opposite to the second active surface and aplurality of second conductive terminals distributed on the secondactive surface, the first conductive terminals and the second conductiveterminals being substantially leveled with each other, and the firstrear surface and the second rear surface face the carrier; forming asecond insulating encapsulation on the de-bonding layer to encapsulatesidewalls of the at least one chip module and sidewalls of the secondintegrated circuit; and forming a redistribution circuit structure onthe at least one chip module, the second insulating encapsulation, andthe second integrated circuit, wherein the redistribution circuitstructure is electrically connected to the first conductive terminalsand the second conductive terminals.
 7. The method of claim 6, whereinthe pre-molded structure comprises the molding compound and the firstintegrated circuits embedded in the molding compound.
 8. The method ofclaim 7 further comprising: grinding the molding compound until athickness of the pre-molded structure is substantially equal to athickness of the second integrated circuit.
 9. The method of claim 8,wherein the first integrated circuits are encapsulated by the moldingcompound and at least parts of the first integrated circuits are exposedafter grinding the molding compound.
 10. The method of claim 8, whereinthe at least one chip module and the second integrated circuit on thecarrier are identical in thickness.
 11. The method of claim 6 furthercomprising: de-bonding the de-bonding layer from the at least one chipmodule, the second integrated circuit, and the second insulatingencapsulation.